Powerful and reliable mainframe CPUs may incorporate duplicate BPUs which work independently to execute the same instruction or instruction series in parallel such that the results can be compared to insure identity. It has now become feasible to incorporate an entire BPU on a single Very Large Scale Integrated (VLSI) circuit which has the advantage of not only occupying less space, but also enjoys the capability to run faster. However, there is a practical limit to the number of conductive leads which can be connected to a VLSI circuit, and this characteristic becomes a problem when double precision data manipulation is performed. This problem arises because each of the duplicate BPUs has typically required a double word result bus which, for example in one computer family in which the present application finds application, means the provision of two 80-bit result buses, one coupled to each BPU. Those skilled in the art will appreciate that it would be highly desirable to obtain reliable double precision results without the necessity to provide double word result buses from each of duplicate BPUs. This has been achieved according to the invention set forth in U.S. patent application Ser. No. 08/065,105 filed May 19, 1993, entitled CENTRAL PROCESSING UNIT USING DUAL BASIC PROCESSING UNITS AND COMBINED RESULT BUS, by Donald C. Boothroyd et al and assigned to the same Assignee as the present application, now United States Patent.
In some critical environments and to further distinguish the fault tolerant performance of a mainframe CPU, particularly in a multi-processor environment, it is desirable to achieve even further confidence in the results of double precision bit manipulations and the integrity of the results. The present invention is directed to this end and to obtaining other desirable results which are a consequence of the implementation of the invention.